High performance microprocessors utilize CMOS process technology. Historically, as CMOS (Complementary Metal Oxide Semiconductor) technology scales to smaller sizes, the energy expended per logic operation decreases, but this decrease slows down as the technology scales below 100 nanometers. In digital logic, the ratio of ON-current (ION) to OFF-current (IOFF) for a transistor is important, where for CMOS logic, ION for a transistor denotes the source-drain current when ON and IOFF denotes the source-drain current when OFF. Unfortunately, this ratio decreases as scaling decreases. This is due to transistors becoming leaky as the technology scales to smaller and smaller sizes. That is, transistors do not actually turn OFF, and the corresponding leakage current is somewhat substantial. Furthermore, as technology scales to smaller dimensions, various transistor characteristics become highly variable, such as threshold voltage, delay, and so forth. In particular, as technology scales below 0.18 microns, the expended power due to leakage, as a percentage of total power consumed, may rise substantially.
Accordingly, it is expected that as technology scales to smaller dimensions, other types of circuit technologies may be needed so that expended power does not become an issue. In this regard, sub-threshold CMOS circuits have been of interest to researchers because in some cases they may be designed as so-called ultra low power circuits. However, in the past, such sub-threshold CMOS circuits have been inadequate for high performance applications.